Given the VAX architecture's age, there already exists plenty of standard and generally accepted terminology. Unfortunately, however, there are certain crucially important concepts in the VAX architecture for which there are no standard terms, and there are some standard terms that are interpreted differently by different people. In order to perform its functions, the Quasijarus Consortium must solve these problems somehow. Given the lack of standard terms for some concepts and the lack of general agreement on the meaning of some standard terms that do exist, there is only one possible solution to this problem: invent some new terms of our own and give some standard terms our own definitions.
Here is the list of official Quasijarus Consortium VAX terms and their definitions. These terms must be used by all Quasijarus Consortium members. It is not a comprehensive list of all VAX terms, only of those defined by the Quasijarus Consortium.
A VAX whose CPU is implemented on a board that plugs into a Q22-bus backplane. This definition is designed to encompass all KA6xx series CPUs.
A VAX whose CPU is implemented on a board that does not plug into a backplane of any kind, instead acting as a motherboard into which options may be inserted. This definition is designed to encompass MicroVAX 2000, VAXstation 2000, MicroVAX/VAXserver 3100, VAXstation 3100, VAX 410x, and VAXstation 4000.
A VAX that is either a Q22-bus MicroVAX or a BabyVAX. No VAX can ever be both a Q22-bus MicroVAX and a BabyVAX, since the two definitions are mutually exclusive.
A VAX in which instruction fetching, decoding, and execution is done by a single integrated circuit. This definition is designed to encompass MicroVAX II, CVAX, SOC, Rigel, Mariah, and NVAX chips.
A device that interfaces one bus to another.
A device that performs some function in and of itself, as opposed to providing an interface for other devices to attach to.
A device that does not do any VAX magic and could be found in a mortal architecture machine.
A device that is designed to attach to the main bus of a VAX and appear in the VAX native 32-bit address space and meets all requirements of the VAX architecture design and the specific VAX implementation it is attached to.
A VAX that does not comply with the two-layer bus structure requirement of the VAX architecture design. See VAX Overview and Classification.
This page has been last updated on 16-MAY-1999.
@(#)defs.html 1.1 03/12/18